ATMEGA169P-16MCU【PDF 72/274 页】MCU AVR 16K ISP FLSH 16MHZ 64QFN

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Sheet目录3828

68页 69页 70页 71页 [72页]73页 74页 75页 76页

2005 Microchip Technology Inc.

Preliminary

DS41265A-page 161

PIC16F946

REGISTER 13-5:

EECON1 – EEPROM CONTROL REGISTER 1 (ADDRESS: 18Ch)

R/W-0

U-0

R/W-x

R/W-0

R/S-0

EEPGD

—

WRERR

WREN

bit 7

bit 0

bit 7

EEPGD: Program/Data EEPROM Select bit

= Accesses program memory

= Accesses data memory

bit 6-4

Unimplemented: Read as ‘0’

bit 3

WRERR: EEPROM Error Flag bit

= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or Brown-out Reset)

= The write operation completed

bit 2

WREN: EEPROM Write Enable bit

= Allows write cycles

= Inhibits write to the data EEPROM

bit 1

WR: Write Control bit

EEPGD = 1:

This bit is ignored

EEPGD = 0:

= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be

set, not cleared, in software.)

= Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit

= Initiates a memory read (RD is cleared in hardware. The RD bit can only be set, not cleared, in

software.)

= Does not initiate an memory read

Legend:

S = Bit can only be set

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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